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Table 27 : Ultra DMA Data Burst Timing Descriptions
Name Comment
t 2CYCTYP Typical sustained average two cycle time
Notes
t CYC
t 2CYC
Cycle time allowing for asymmetry and clock variations (from STROBE edge to STROBE edge)
Two cycle time allowing for clock variations (from rising edge to next rising edge or from
falling edge to next falling edge of STROBE)
t DS
t DH
t DVS
t DVH
t CS
t CH
t CVS
t CVH
t ZFS
T DZFS
T FS
t LI
t MLI
t UI
t AZ
t ZAH
t ZAD
t ENV
t RFS
t RP
t IORDYZ
t ZIORDY
t ACK
t SS
Data setup time at recipient (from data valid until STROBE edge)
Data hold time at recipient (from STROBE edge until data may become invalid)
Data valid setup time at sender (from data valid until STROBE edge)
Data valid hold time at sender (from STROBE edge until data may become invalid)
CRC word setup time at device
CRC word hold time device
CRC word valid setup time at host (from CRC valid until – DMACK negation)
CRC word valid hold time at sender (from – DMACK negation until CRC may become invalid)
Time from STROBE output released-to-driving until the first transition of critical timing.
Time from data output released-to-driving until the first transition of critical timing.
First STROBE time (for device to first negate DSTROBE from STOP during a data in burst)
Limited interlock time
Interlock time with minimum
Unlimited interlock time
Maximum time allowed for output drivers to release (from asserted or negated)
Minimum delay time required for output
drivers to assert or negate (from released)
Envelope time (from – DMACK to STOP and – HDMARDY during data in burst initiation and
from DMACK to STOP during data out burst initiation)
Ready-to-final-STROBE time (no STROBE edges shall be sent this long after negation of
-DMARDY)
Ready-to-pause time (that recipient shall wait to pause after negating – DMARDY)
Maximum time before releasing IORDY
Minimum time before driving IORDY
Setup and hold times for – DMACK (before assertion or negation)
Time from STROBE edge to negation of DMARQ or assertion of STOP (when sender terminates
2, 5
2, 5
3
3
2
2
3
3
1
1
1
4
a burst)
Notes:
1.
2.
The parameters t UI , t MLI (in Figure 13: Ultra DMA Data-In Burst Device Termination Timing and Figure 14:
Ultra DMA Data-In Burst Host Termination Timing), and t LI indicate sender-to-recipient or recipient-to-
sender interlocks, i.e., one agent (either sender or recipient) is waiting for the other agent to respond
with a signal before proceeding. T UI is an unlimited interlock that has no maximum time value. T MLI is a
limited time-out that has a defined minimum. T LI is a limited time-out that has a defined maximum.
80-conductor cabling shall be required in order to meet setup (t DS , t CS ) and hold (t DH , t CH ) times in modes
greater than 2.
3. Timing for t DVS , t DVH , t CVS and t CVH shall be met for lumped capacitive loads of 15 and 40 pF at the connector
where the Data and STROBE signals have the same capacitive load value. Due to reflections on the cable,
these timing measurements are not valid in a normally functioning system.
4. For all modes the parameter t ZIORDY may be greater than t ENV due to the fact that the host has a pull-up on
IORDY- giving it a known state when released.
5. The parameters t DS , and t DH for mode 5 are defined for a recipient at the end of the cable only in a
configuration with a single device located at the end of the cable. This could result in the minimum
values for t DS and t DH for mode 5 at the middle connector being 3.0 and 3.9 ns respectively.
Swissbit AG
Industriestrasse 4
Swissbit reserves the right to change products or specifications without notice.
Revision: 1.00
CH-9552 Bronschhofen
Switzerland
www.swissbit.com
industrial@swissbit.com
C-440_data_sheet_CF-HxBU_Rev100.doc
Page 29 of 102
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